1. Field of the Invention
The present invention relates to a semiconductor circuit, and more particularly to a semiconductor circuit which is used as an input buffer for interconnection between large scale integration circuits.
2. Description of the Related Art
As a semiconductor circuit of the type mentioned, a differential amplification circuit is conventionally used to achieve a high speed interface operation.
An NMOS differential amplification circuit which employs an NMOS transistor amplifies, if a signal of a false emitter coupled logic (ECL) level is applied to an input terminal, the signal and outputs a signal of a complementary metal oxide semiconductor (CMOS) level (hereinafter referred to as first prior art).
The circuit of the first prior art described above exhibits a small delay when the level of the input signal is proximate to a power supply voltage like a signal of the false ECL level. However, the first prior art circuit is disadvantageous in that, when the level of the input signal is proximate to a reference voltage like a gunning transfer logic (GTL) level, it exhibits a large delay time because the operating current is low.
Meanwhile, a PMOS differential amplification circuit which employs a PMOS transistor receives a signal of the GTL level at an input terminal thereof and outputs a signal of the CMOS level (hereinafter referred to as second prior art).
The circuit of the second prior art just described exhibits a small delay time when the level of the input signal is proximate to the GTL level. However, the second prior art circuit is disadvantageous in that it exhibits a large delay time when the level of the input signal is proximate to a power supply voltage like a signal of the false ECL level.
A further semiconductor circuit of the type described is disclosed in Japanese Patent Laid-Open Application No. Heisei 5-48430 and is shown in FIG. 7.
Referring to FIG. 7, the semiconductor circuit includes a PMOS differential circuit 1100 and an NMOS differential circuit 1200 whose output terminals are connected to an output line 1140. A pair of inverters 1150 and 1160 are connected in a cascade connection to the output line 1140 so that an output signal may be obtained through the inverters 1150 and 1160 (hereinafter referred to as third prior art).
Referring also to FIG. 8, with the semiconductor circuit of the third prior art, since the output terminal of the PMOS differential circuit 1100 and the output terminal of the NMOS differential circuit 1200 are connected to the output line 1140, even if a signal which oscillates between the ground level GND and a power supply voltage is inputted to each of the input terminals, the signal outputted from the output line 1140 does not exhibit oscillations between the ground level and the power supply voltage. Consequently, the semiconductor circuit is disadvantageous in that, in the inverter 1150 connected to the output line 1140, through-current flows from a power supply terminal to the ground and increases the power dissipation as much.
Further, since also the output signal of the inverter 1150 does not oscillate between the ground level and the power supply voltage, it must be inputted to the additional inverter 1160. In this manner, the third prior art circuit is disadvantageous in that, in order to obtain an output signal which oscillates between the ground level and the power supply voltage, an additional inverter must be provided and this has a bad influence on high speed operation.